1. Field of the Disclosure
Generally, the present disclosure relates to integrated circuits and methods for the formation thereof, and, in particular, to integrated circuits including field effect transistors having stress creating regions and methods for the formation thereof.
2. Description of the Related Art
Integrated circuits include a large number of circuit elements which include, in particular, field effect transistors. In a field effect transistor, a gate structure including a gate electrode and a gate insulation layer may be provided, wherein the gate insulation layer separates the gate electrode from a channel region and provides an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region may be provided. The source region, the drain region and the channel region may be provided in a semiconductor material, wherein the source region and the drain region are doped differently than the channel region. In P-channel transistors, the source and drain regions may be P-doped, and the channel region may be N-doped or substantially undoped. In N-channel transistors, the source region and the drain region may be N-doped, and the channel region may be P-doped or substantially undoped.
Depending on a gate voltage that is applied between the gate electrode and the source region, a field effect transistor can be switched between an ON-state, wherein there is a relatively high electrical conductance between the source region and the drain region, and an OFF-state, wherein there is a relatively low electrical conductance between the source region and the drain region. The conductance of the channel region in the ON-state of the field effect transistor may depend on the dopant concentration in the channel region, the mobility of charge carriers in the channel region, the extension of the channel region in the width direction of the transistor and on the distance between the source region and the drain region, which is commonly denoted as “channel length.”
For increasing the conductance of the channel region in the ON-state of the transistor, it has been proposed to improve the mobility of charge carriers in the channel region by modifying the lattice structure of the semiconductor material wherein the channel region is formed. This may be done by creating a tensile or compressive stress in the channel region. A compressive stress in the channel region can increase the mobility of holes, leading to an increase of the conductivity of the channel region of P-type transistors. Conversely, a tensile stress in the channel region can increase the mobility of electrons, which can improve the conductivity of the channel region of N-type transistors.
For creating a compressive stress in the channel region of a P-channel transistor having a channel region that is provided in a silicon semiconductor material, stress creating regions including silicon germanium may be formed adjacent the channel region of the transistor. For forming the stress creating regions, recesses may be formed in the substrate adjacent the channel region, and the recesses may be filled with silicon germanium. Silicon germanium has a greater crystal lattice constant than substantially pure silicon. When silicon germanium is deposited on substantially pure silicon, the differences in the crystal lattice constants between silicon germanium and silicon can create a compressive stress.
In some examples of P-channel transistors including silicon germanium stress creating regions, a so-called sigma shape of the interface between the stress creating regions and the channel regions may be provided, wherein the interface includes an upper portion that is inclined inwardly relative to the channel region, and a lower portion that is inclined outwardly relative to the channel region, similar to the shape of the Greek letter “Σ” For obtaining the sigma shape of the interface between the silicon germanium and the silicon, U-shaped recesses may be formed adjacent the gate structure of the transistor by means of a reactive ion etch process. Thereafter, a crystallographic wet etch process, for example, a wet etch process wherein an etchant including tetramethylammoniumhydroxide (TMAH) is used, may be performed. The crystallographic wet etch process may have a substantially greater etch rate in the <100> crystal direction of silicon than in the <111> crystal direction. Therefore, in the wet etch process, surfaces being normal to <111> directions can be obtained, which may provide inwardly inclined upper and outwardly inclined lower portions of sidewalls of the recesses, which can provide the sigma shape of the stress creating regions when the recesses are filled with silicon germanium.
The compressive stress obtained in the channel region of the transistor can depend on a distance of a tip between the upper and lower portions of the interface between the stress creating regions and the channel region from the gate insulation layer and on a tip-to-tip distance between the tip of the stress creating region at the source-side of the gate structure and the tip of the stress creating region at the drain-side of the gate structure.
In some applications of stress creating regions as described above, it may be desirable to obtain a greater stress in the channel regions of transistors.
The present disclosure provides semiconductor structures including transistors having a relatively high stress in their channel regions and methods for the formation thereof.